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 Altera USB Blaster Cable For CPLD FPGA NIOS JTAG
Altera USB Blaster Cable For CPLD FPGA NIOS JTAG
Stock : 13pcs
Price:PKR 950.00

For demo video click here:

Supported target voltage : 1.0V-5.5V.
Support all ALTERA device.
CPLD:MAX 3000A?MAX 7000A?MAX 7000B?MAX 7000S?MAX 9000?MAX 9000A and MAX II.
FPGA:Stratix?Stratix II?Stratix GX?Cyclone?Cyclone II?Cyclone III?ACEX 1K?APEX II?APEX 20K?APEX 20KE?APEX 20KC?FLEX 10K?FLEX 10KE?FLEX 10KA?FLEX 6000?FLEX 8000?EPCS1?EPCS4?EPCS16?EPCS64EPC1?EPC4?EPC8?EPC16.
Support:JTAG, AS, PS Mode.
Support NiosII embeded core based debug.
Supports Quartus II Signal Tap? II Logic Analyzer (for logic analysis).
High performance, 6 times faster than ByteBlasterII.
USB interface with status and Power LED.
Size:5.5cm x 2.8cm x 1.5cm - 2.17inch x 1.1inch x 0.59inch.

Altera's USB-Blaster Download Cable interfaces a USB port on a host computer to an Altera FPGA mounted on a printed circuit board.

The cable sends configuration data from the PC to a standard 10-pin header connected to the FPGA. You can use the USB-Blaster cable to iteratively download configuration data to a system during prototyping or to program data into the system during production.

Stratix series FPGAs
Cyclone series FPGAs
MAX series CPLDs
Arria GX series FPGAs
APEX series FPGAs
Mercury FPGAs
FLEX 10K series FPGAs
Excalibur FPGAs
Altera configuration devices including EPC2 devices
Enhanced configuration devices including EPC4, EPC8, and EPC16 devices
Serial configuration devices including EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128 devices
In addition, you can perform SignalTap II logic analysis
The USB-Blaster download cable supports target systems using 5.0-V TTL, 3.3-V LVTTL/LVCMOS, and single-ended I/O standards from 1.5 V to 3.3 V
5.0 V from the USB cable
Between 1.5 V and 5.0 V from the target circuit board
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